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PRELIMINARY
CY7C1361V25 CY7C1363V25 CY7C1365V25
256K x 36/256K x 32/512K x 18 Flowthrough SRAM
Features
* Supports 113-MHz bus operations * 256K x 36 / 256K x 32 / 512K x 18 common I/O * Fast clock-to-output times -- 7.5 ns (for 117-MHz device) -- 8.5 ns (for 100-MHz device) -- 10.0 ns (for 80-MHz device) * Two-bit wrap-around counter supporting either interleaved or linear burst sequences * Separate processor and controller address strobes provide direct interface with the processor and external cache controller * Synchronous self-timed writes * Asynchronous output enable * Single 2.5V Power supply * JEDEC-standard pinout * Available as a 100-pin TQFP or 119 BGA * "ZZ" Sleep Mode option flowthrough SRAM designed to interface with high-speed microprocessors with minimal glue logic. Maximum access delay from the clock rise is 7.5 ns (117-MHz device). A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. The CY7C1361V25/CY7C1365V25/CY7C1363V25 supports either the interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. Byte write operations are qualified with the Byte Write Select (BWa,b,c,d for CY7C1361V25/CY7C1365V25 and BWa,b for CY7C1363V25) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output three-state control.
Functional Description
The CY7C1361V25, CY7C1365V25 and CY7C1363V25 are 2.5v, 256K x 36, 256K x 32 and 512K x 18 synchronous-
Logic Block Diagram
CLK ADV Ax GW CE1 CE2 CE3 BWE BWx MODE ADSP ADSC ZZ OE CONTROL and WRITE LOGIC 256Kx36/ 512Kx18 MEMORY ARRAY CE
Data-In REG.
D Q
DQx DPx
AX DQX DPX BWX
7C1361/65 A[17:0] DQa,b,c,d DPa,b,c,d BWa,b,c,d
7C1363 A[18:0] DQa,b,c,d DPa,b BWa,b
Selection Guide
7C1361-133 7C1365-133 7C1363-133 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA)
Shaded areas contain advance information.
7C1361-117 7C1365-117 7C1363-117 7.5 300 10
7C1361-100 7C1365-100 7C1363-100 8.5 260 10
7C1361-80 7C1365-80 7C1363-80 10.0 210 10
6.5 Commercial 350 10
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
* 408-943-2600 December 1, 1999
PRELIMINARY
Pin Configurations
100-Pin TQFP
A A CE 1 CE 2 BWd BWc BWb BWa CE 3 V DD V SS CLK GW BWE OE ADSC ADSP ADV A A
CY7C1361V25 CY7C1363V25 CY7C1365V25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC,DPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc VSS VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd NC,DPd
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1361/1365 (256K X 36/256K x 32)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC,DPb DQb DQb VDDQ VSSQ DQb DQb DQb DQb VSSQ VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa DQa DQa VSSQ VDDQ DQa DQa NC,DPa
NC NC NC VDDQ VSSQ NC NC DQb DQb VSSQ VDDQ DQb DQb VSS VDD NC VSS DQb DQb VDDQ VSSQ DQb DQb DPb NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWb BWa CE3 V DD V SS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1363 (512K x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DPa DQa DQa VSSQ VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSSQ DQa DQa NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 DNU DNU V SS V DD
MODE A A A A A1 A0 DNU DNU VSS V DD
DNU A A A A A A A A
2
DNU A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PRELIMINARY
Pin Configurations (continued)
119-Ball BGA
CY7C1361/CY7C1365 (256K x 36, 256K x 32) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ c DQ c VDDQ DQ c DQ c VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CE2 A NC,DPc DQc DQc DQc DQc VDD DQd DQd DQd DQd NC,DPd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS VSS A TDO 6 A A A NC,DPb DQb DQb DQb DQb VDD DQa DQa DQa DQa NC,DPa A NC DNU 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
CY7C1361V25 CY7C1363V25 CY7C1365V25
CY7C1363 (512K x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ b NC VDDQ NC DQ b VDDQ NC DQ b VDDQ DQ b NC NC NC VDDQ 2 A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DPb A A TMS 3 A A A VSS VSS VSS BWb VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWa VSS VSS VSS VSS A TDO 6 A A A DPa NC DQa NC DQb VDD NC DQa NC DQa NC A A DNU 7 VDDQ NC NC NC DQ a VDDQ DQ a NC VDDQ DQ a NC VDDQ NC DQ a NC ZZ VDDQ
3
PRELIMINARY
Pin Definitions (100-Pin TQFP)
x18 Pin Location 37, 36, 32-25, 43-50, 80-82, 99, 100 93, 94 x36 Pin Location 37, 36, 32-35, 43-50, 81, 82, 99, 100 93, 94, 95, 96 Name A0 A1 A BWa BWb BWc BWd GW I/O InputSynchronous
CY7C1361V25 CY7C1363V25 CY7C1365V25
Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE 2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Selects burst order. When tied to GND selects linear burst sequence. When tied to V DDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
InputSynchronous
88
88
InputSynchronous
87
87
BWE
InputSynchronous Input-Clock
89
89
CLK
98
98
CE1
InputSynchronous
97
97
CE2
InputSynchronous InputSynchronous InputAsynchronous
92
92
CE3
86
86
OE
83
83
ADV
InputSynchronous InputSynchronous
84
84
ADSP
85
85
ADSC
InputSynchronous
31
31
MODE
InputStatic
4
PRELIMINARY
Pin Definitions (100-Pin TQFP) (continued)
x18 Pin Location 64 x36 Pin Location 64 Name ZZ I/O InputAsynchronous I/OSynchronous
CY7C1361V25 CY7C1363V25 CY7C1365V25
Description ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. On the CY7C1365 SRAM, these are not connect pins. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQa-DQd and DPa-DPd are placed in a three-state condition. Power supply inputs to the core of the device. Should be connected to 2.5V power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 2.5V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. No Connects.
(a)58, 59, 62, 63, 68, 69, 72, 73 (b)8, 9, 12, 13, 18, 19, 22, 23
(a)52, 53, 56-59, 62, 63 (b)68, 69, 72-75, 78, 79 (c)2, 3, 6-9, 12, 13 (d)18, 19, 22-25, 28, 29
NC,DQ a NC,DQ b NC,DQ c NC,DQ d
74, 24
51, 80, 1, 30
DPa DPb DPc DPd
I/OSynchronous
15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96 42 38, 39
15, 41, 65, 91 17, 40, 67, 90 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 21, 26, 55, 60, 71, 76 16, 66
VDD VSS VDDQ VSSQ NC
Power Supply Ground I/O Power Supply I/O Ground -
42 38, 39
DNU DNU
Do Not Use Pins. This pin is used for the address expansion to the next density SRAM. Do Not Use Pins. These pins should be left floating or tied to VSS.
5
PRELIMINARY
Pin Definitions (119-Ball BGA)
x18 Pin Location 4P, 4N, 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6B, 6T 5L, 3G x36 Pin Location 4P, 4N, 2A, 2C, 2R, 3A, 3B, 3C, 3T, 4T, 5A, 5B, 5C, 5T, 6A, 6B, 6C, 6R 5L, 5G, 3G, 3L Name A0 A1 A I/O InputSynchronous
CY7C1361V25 CY7C1363V25 CY7C1365V25
Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. This pin will be used for address expansion to the next density SRAM. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
BWa BWb BWc BWd GW
InputSynchronous
4M
4M
InputSynchronous
4H
4H
BWE
InputSynchronous Input-Clock
4K
4K
CLK
4E
4E
CE1
InputSynchronous
97
97
CE2
InputSynchronous
92
92
CE3
InputSynchronous InputAsynchronous
4F
4F
OE
4G
4G
ADV
InputSynchronous InputSynchronous
4A
4A
ADSP
4B
4B
ADSC
InputSynchronous
6
PRELIMINARY
Pin Definitions (119-Ball BGA) (continued)
x18 Pin Location 3R x36 Pin Location 3R Name MODE I/O InputStatic
CY7C1361V25 CY7C1363V25 CY7C1365V25
Description Selects burst order. When tied to GND selects linear burst sequence. When tied to V DDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. On the CY7C1365 SRAM, these are not connect pins. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQa-DQb and DPa-DPd are placed in a three-state condition. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
7T
7T
ZZ
InputAsynchronous I/OSynchronous
(a)6F, 6H, 6L, 6N, 7E, 7G, 7K, 7P (b)1D, 1H, 1L, 1N, 2E, 2G, 2K, 2M
(a)6K, 6L, 6M, 6N, 7K, 7L, 7N, 7P (b)6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H (c)1D, 1E, 1G, 1H, 2E, 2F, 2G, 2H (d)1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N
NC,DQ a NC,DQ b NC,DQ c NC,DQ d
6D, 2P
6P, 6D, 2D, 2P
DPa DPb DPc DPd
I/OSynchronous
U5
U5
TDO
JTAG Serial Output, Synchronous JTAG Serial Input, Synchronous
U3
U3
TDI
U2 U4 2J, 4C, 4J, 4R, 5R, 6J 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H. 5K, 5M, 5N, 5P
U2 U4 2J, 4C, 4J, 4R, 5R, 6J 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H. 5K, 5M, 5N, 5P
TMS TCK VDD VSS
Test Mode Select, This pin controls the Test Access Port state maSynchronous chine. Sampled on the rising edge of TCK. JTAG-Clock Power Supply Ground Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Should be connected to 2.5V power supply. Ground for the device. Should be connected to ground of the system.
1A, 1F, 1J, 1M, 1U, 1A, 1F, 1J, 1M, 1U, 7A, 7F, 7J, 7M, 7U 7A, 7F, 7J, 7M, 7U 1B, 1C, 1E, 1G, 1K, 1P, 1R, 1T, 2D, 2F, 2H, 2L, 2N, 3J, 4D, 4L, 4T, 5J, 6E, 6G, 6K, 6M, 6P, 6U, 7B, 7C, 7D, 7H, 7L, 7N, 7R 6U 1B, 1C, 1R, 1T, 2T, 3J, 4D, 4L, 5J, 6T, 6U, 7B, 7C, 7R
VDDQ NC
I/O Power Supply -
Power supply for the I/O circuitry. Should be connected to a 2.5V power supply. No Connects.
6U
DNU
Do Not Use Pins. These pins should be left floating.
7
PRELIMINARY
Functional Description
Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BWx) and ADV inputs are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. The CY7C1361V25/CY7C1365V25/CY7C1363V25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWa,b,c,d for CY7C1361V25/ CY7C1365V25 and BWa,b for CY7C1363V25) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. All I/Os are threestated during a byte write. Because the CY7C1361V25/CY7C1365V25/CY7C1363V25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE 2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWx) are asserted active to conduct a write to the desired byte(s). ADSC is ignored if ADSP is active LOW. The address presented to A[18:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQx is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation
CY7C1361V25 CY7C1363V25 CY7C1365V25
will remain unaltered. All I/Os are three-stated during a byte write. Because the CY7C1361V25/CY7C1365V25/CYC7C1363V25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers. As a safety precaution, DQx are automatically three-stated whenever a write cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1361V25/CY7C1365V25/CY7C1363V25 provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.
Interleaved Burst Sequence
First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00
Linear Burst Sequence
First Address A[1:0] 00 01 10 11 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ HIGH places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Leaving ZZ unconnected defaults the device into an active state. Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10
8
PRELIMINARY
ZZ Mode Electrical Characteristics
Parameter ICCZZ tZZS tZZREC Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V 2tCYC Min Max 15 2tCYC
CY7C1361V25 CY7C1363V25 CY7C1365V25
Unit mA ns ns
Cycle Descriptions[1, 2, 3]
Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ "sleep" Add. Used None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current None ZZ L L L L L L L L L L L L L L L L L L L L L L H CE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X X CE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X X CE1 1 0 0 0 0 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 X ADV X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 X OE X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write X
Note: 1. X = "don't care", 1 = HIGH, 0 = LOW. 2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWx. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a "Don't Care" for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ = High-Z when OE is inactive or when the device is deselected, and DQ = data when OE is active.
9
PRELIMINARY
Write Cycle Description[1, 2, 3]
Function (1361/1365) Read Read Write Byte 0 - DQa Write Byte 1 - DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes Function (1363) Read Read Write Byte 0 - DQa and DPa Write Byte 1 - DQb and DPb Write All Bytes Write All Bytes GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 GW 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X BWd X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X BWE 1 0 0 0 0 X BWc X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BWb X 1 1 0 0 X
CY7C1361V25 CY7C1363V25 CY7C1365V25
BWb X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X
BWa X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X BWa X 1 0 1 0 X
10
PRELIMINARY
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1361/63 incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port (TAP) - Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register. Test Data Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (See TAP Controller State Diagram). The output changes on the falling edge of TCK. TDO is connected to the Least Significant Bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuit-
CY7C1361V25 CY7C1363V25 CY7C1365V25
ry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in the TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the CaptureIR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The x36 configuration has a xx-bit-long register, and the x18 configuration has a yy-bit-long register. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address, data, or control signals into the
11
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE / PRELOAD; rather it performs a capture of the Inputs and Output ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the TAP controller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE / PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE / PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE / PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1 compliant.
CY7C1361V25 CY7C1363V25 CY7C1365V25
When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. Note that since the PRELOAD part of the command is not implemented, putting the TAP into the Update to the UpdateDR state while performing a SAMPLE / PRELOAD instruction will have the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
12
PRELIMINARY
TAP Controller State Diagram
CY7C1361V25 CY7C1363V25 CY7C1365V25
1
TEST-LOGIC RESET 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-DR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0
0
TEST-LOGIC/ IDLE
1
SELECT DR-SCAN 0 1
1
Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
13
PRELIMINARY
TAP Controller Block Diagram
CY7C1361V25 CY7C1363V25 CY7C1365V25
0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO
2 Instruction Register
1
0
31 30
29
.
.
2
1
0
Identification Register
x
.
.
.
.
2
1
0
Boundary Scan Register
TCK TAP Controller TMS
TAP Electrical Characteristics Over the Operating Range[4, 5]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VI < VDDQ IOH = -2.0 mA IOH = -100 mA IOL = 2.0 mA IOL = 100 mA 1.7 -0.3 -5 Test Conditions Min. 1.7 2.1 0.7 0.2 VDD+0.3 0.7 5 Max. Unit V V V V V V mA
Notes: 4. All Voltage referenced to Ground. 5. Overshoot: VIH(AC)14
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[6, 7]
Parameter tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 10 10 10 TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 40 40 Description Min. 100
CY7C1361V25 CY7C1363V25 CY7C1365V25
Max. 10
Unit ns MHz ns ns ns ns ns ns ns ns
20
ns ns
Notes: 6. t CS and t CH refer to the set-up and hold time requirements of latching data from the boundary scan register. 7. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
15
PRELIMINARY
TAP Timing and Test Conditions
CY7C1361V25 CY7C1363V25 CY7C1365V25
1.25V 50 TDO Z0 =50 CL =20pF 0V ALL INPUT PULSES 2.5V 1.25V
GND
(a)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI
Test Data-Out TDO
tTDOX
tTDOV
16
PRELIMINARY
Identification Register Definitions
Instruction Field Revision Number (31:28) Device Depth (27:23) Device Width (22:18) Cypress Device ID (17:12) Cypress JEDEC ID (11:1) ID Register Presence (0) TBD TBD TBD TBD TBD TBD Value Description Reserved for version number Defines depth of SRAM Defines with of the SRAM Reserved for future use
CY7C1361V25 CY7C1363V25 CY7C1365V25
Allows unique identification of SRAM vendor Indicate the presence of an ID register
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan 3 1 32 TBD Bit Size
Identification Codes
Instruction EXTEST 000 Code Description Captures the Input/Output ring contents. Places the boundary scan register between the TDI and TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload function and is therefore not 1149.1 compliant. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD
001 010 011 100
RESERVED RESERVED BYPASS
101 110 111
17
PRELIMINARY
Boundary Scan Order
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
CY7C1361V25 CY7C1363V25 CY7C1365V25
Boundary Scan Order
Bit # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bit # Signal Name TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Bump ID TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
18
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines only, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +3.6V DC Voltage Applied to Outputs in High Z State[9] ................................. -0.5V to VDDQ + 0.5V
CY7C1361V25 CY7C1363V25 CY7C1365V25
DC Input Voltage[9] .............................. -0.5V to VDDQ + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
.
Operating Range
Range Com'l Ambient Temperature[8] 0C to +70C VDD/VDDQ 2.5V 5%
Electrical Characteristics Over the Operating Range
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage
[9]
Test Conditions
Min. 2.375 2.375
Max. 2.625 2.625 0.2
Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA
VDD = Min., IOH = -1.0 mA VDD = Min., IOL = 1.0 mA
2.0 1.7 -0.3 VDD + 0.3V 0.7 5 30 30 -1.0 7.5-ns cycle, 133 MHz 8.8-ns cycle, 113 MHz 10-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz 1.0 350 300 260 210 90 80 70 65 10
Input Load Current except ZZ and MODE Input Current of MODE Input Current of ZZ
GND < VI < VDDQ
-5 -30
Input = VSS Input = VDDQ GND < VI < VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC
-5
IOZ IDD
Output Leakage Current VDD Operating Supply Current
ISB1
Automatic CS Power-Down Current--TTL Inputs
Max. V DD, Device Deselected, VIN > V IH or VIN < VIL f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz 8.8-ns cycle, 113 MHz 10-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz
ISB2
Automatic CS Max. V DD, Device Deselected, Power-Down VIN < 0.3V or V IN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 Automatic CS Max. VDD, Device Deselected, or Power-Down VIN < 0.3V or VIN > VDDQ - 0.3V Current--CMOS Inputs f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 8.8-ns cycle, 113 MHz 10-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz
ISB3
45 40 35 30 25
mA mA mA mA mA
ISB4
Automatic CS Power-Down Current--TTL Inputs
Max. V DD, Device Deselected, VIN > V IH or VIN < VIL, f = 0
Shaded areas contain advance information. Notes: 8. TA is the case temperature. 9. Minimum voltage equals -2.0V for pulse durations of less than 20 ns.
19
PRELIMINARY
Capacitance[10]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = VDDQ = 2.5V Max. 4 4 4
CY7C1361V25 CY7C1363V25 CY7C1365V25
Unit pF pF pF
AC Test Loads and Waveforms
OUTPUT Z0 = 50 RL = 50 VL = 1.25V 2.5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R = 1667 ALL INPUT PULSES 2.5V 10% GND R = 1538 2.0 ns 90%
[11]
90% 10% 2.0 ns
(a)
(b)
(c)
Notes: 10. Tested initially and after any design or process changes that may affect these parameters. 11. Input waveform should have a slew rate of > 1 V/ns.
20
PRELIMINARY
Switching Characteristics Over the Operating Range[12, 13, 14]
-133 Parameter tCYC tCH tCL tAS tAH tCO tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Description Clock Cycle Time Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP, ADSC Set-Up Before CLK Rise ADSP, ADSC Hold After CLK Rise BWE, GW, BW[3:0] Set-Up Before CLK Rise BWE, GW, BW[3:0] Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip enable Set-Up Chip enable Hold After CLK Rise Clock to High-Z Clock to Low-Z
[13, 14, 15]
CY7C1361V25 CY7C1363V25 CY7C1365V25
-117 Min. 8.5 3.0 3.0 2 0.5 6.5 7.5 1.5 2 0.5 2 0.5 2.0 0.5 2.0 0.5 2 0.5 3.5 0 0 3.5 3.5 0 3.5 4.2 0 3.5 1.5 2 0.5 2 0.5 2.0 0.5 2.0 0.5 2 0.5 0 0 Max.
-100 Min. 10.0 3.2 3.2 2 0.5 8.5 1.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 3.5 0 0 3.5 0 5.0 Max. Min. 12.5 4.0 4.0 2.0 0.5
-80 Max. Unit ns ns ns ns ns 10.0 ns ns ns ns ns ns ns ns ns ns ns ns 3.5 ns ns 3.5 ns ns 5.0 ns
Min. 7.5 1.9 1.9 1.5 0.5
Max.
1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 0 0
[13, 14, 15]
OE HIGH to Output High-Z[13, 14] OE LOW to Output Low-Z OE LOW to Output Valid
[13, 14]
0
[13, 14]
Notes: 12. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified I OL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads. 13. t CHZ, tCLZ, t OEV, tEOLZ , and t EOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 200 mV from steadystate voltage. 14. At any given voltage and temperature, tCHZ (max.) is less than tCLZ (min.). 15. This parameter is sampled and not 100% tested.
21
PRELIMINARY
Timing Diagrams
Write Cycle Timing[16, 17]
CY7C1361V25 CY7C1363V25 CY7C1365V25
Single Write tCH tCYC
Burst Write
Pipelined Write Unselected
CLK
tADH tADS tCL ADSP ignored with CE1 inactive
ADSP
tADS tADH
ADSC initiated write
ADSC
tADVS tADVH
ADV
tAS
ADV Must Be Inactive for ADSP Write
WD1 tAH WD2 WD3
ADD
GW
tWS tWH tWS CE1 masks ADSP tWH
WE
tCES tCEH
CE1
tCES tCEH Unselected with CE2
CE2
CE3
tCES tCEH
OE
tDS
tDH High-Z
Data- High-Z In
1a 1a
2a = UNDEFINED
2b
2c
2d
3a
= DON'T CARE
Notes: 16. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table). 17. WDx stands for Write Data to Address X.
22
PRELIMINARY
Timing Diagrams (continued)
Read Cycle Timing [16, 18]
CY7C1361V25 CY7C1363V25 CY7C1365V25
Single Read tCYC
Burst Read tCH Unselected Pipelined Read
CLK
tADS tADH tCL ADSP ignored with CE1 inactive
ADSP
tADS ADSC initiated read
ADSC
tADVS tADH tADVH RD1 tAH RD2 RD3 Suspend Burst
ADV
tAS
ADD
GW
tWS
tWH
tWS
WE
tCES tCEH tWH CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES tCEH
CE3
tCES tCEH tEOV tCDV tOEHZ 2a tCLZ tCHZ = DON'T CARE = UNDEFINED
OE
tDOH 2b 2c 2c 2d 3a
Data Out
1a 1a
Note: 18. RDx stands for Read Data from Address X.
23
PRELIMINARY
Timing Diagrams (continued)
Read/Write Timing tCH tCYC tCL
CY7C1361V25 CY7C1363V25 CY7C1365V25
CLK
tAH
B C D
tAS
ADD
A
tADS
tADH
ADSP
tADS tADH
ADSC
tADVS tADVH
ADV
tCES tCEH
CE1
tCES tCEH
CE
tWES tWEH
WE
ADSP ignored with CE1 HIGH tEOHZ
Q(A) Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D)
OE
tCLZ
Data In/Out
tCDV
tDOH tCHZ
Device originally deselected
WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON'T CARE = UNDEFINED
24
PRELIMINARY
Timing Diagrams (continued)
Pipeline Timing tCH tCYC tCL
CY7C1361V25 CY7C1363V25 CY7C1365V25
CLK
tAS
ADD
RD1
RD2
RD3
RD4
WD1
WD2
WD3
WD4
tADS
ADSC initiated Reads
tADH
ADSC
ADSP initiated Reads
ADSP
ADV
tCES tCEH
CE1
CE
tWES tWEH
WE
ADSP ignored with CE1 HIGH
OE
tCLZ
Data In/Out
tCDV
1a Out
2a Out
3a Out
4a Out
1a In
2a In tDOH
3a In
4a D(C) In
Back to Back Reads
tCHZ Back to Back Writes
= DON'T CARE
= UNDEFINED
25
PRELIMINARY
Timing Diagrams (continued)
OE Switching Waveforms
CY7C1361V25 CY7C1363V25 CY7C1365V25
OE
tEOHZ tEOV
I/Os
Three-State
tEOLZ
26
PRELIMINARY
Timing Diagrams (continued)
ZZ Mode Timing [19, 20]
CY7C1361V25 CY7C1363V25 CY7C1365V25
CLK
ADSP
HIGH
ADSC CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
ICC
ICC(active) ICCZZ
tZZREC
I/Os Three-state
Notes: 19. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device. 20. I/Os are in three-state when exiting ZZ sleep mode.
27
PRELIMINARY
Ordering Information
Speed (MHz) 133 117 100 80 133 117 100 80 133 117 100 80 133 117 100 80 133 117 100 80 133 117 100 80 Ordering Code CY7C1361V25-133AC CY7C1361V25-117AC CY7C1361V25-100AC CY7C1361V25-80AC CY7C1363V25-133AC CY7C1363V25-117AC CY7C1363V25-100AC CY7C1363V25-80AC CY7C1365V25-133AC CY7C1365V25-117AC CY7C1365V25-100AC CY7C1365V25-80AC CY7C1361V25-133BGC CY7C1361V25-117BGC CY7C1361V25-100BGC CY7C1361V25-80BGC CY7C1363V25-133BGC CY7C1363V25-117BGC CY7C1363V25-100BGC CY7C1363V25-80BGC CY7C1365V25-133BGC CY7C1365V25-117BGC CY7C1365V25-100BGC CY7C1365V25-80BGC BG119 119-Ball BGA BG119 119-Ball BGA BG119 119-Ball BGA A101 100-Lead Thin Quad Flat Pack A101 100-Lead Thin Quad Flat Pack Package Name A101 Package Type 100-Lead Thin Quad Flat Pack
CY7C1361V25 CY7C1363V25 CY7C1365V25
Operating Range Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Shaded areas contain advance information.
Document #: 38-00761-P
28
PRELIMINARY
CY7C1361V25 CY7C1363V25 CY7C1365V25
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
29
PRELIMINARY
Package Diagrams (continued)
CY7C1361V25 CY7C1363V25 CY7C1365V25
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Revision History
Document Title: CY7C1361V25/CY7C1363V25/CY7C1365V25 Document Number: 38-00761 REV. ** *A ECN NO. 2561 2684 ISSUE DATE 4/29/99 9/10/99 ORIG. OF CHANGE SKX SKX DESCRIPTION OF CHANGE 1. New Data Sheet 1. Updated the BGA pinout 2. Added revision history
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

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